1. Field of the Invention
The method and system of the present invention relate to the organization of multicomputer systems having a system bus which is common to a number of modules as well as additional bus systems which are local to the modules.
2. Description of the Prior Art
To improve system performance, multicomputer systems have buffer memories linked to each processor, usually called caches. To simplify programming, various measures, called cache coherence for example as described in the book "Computer Architecture--A Quantitative Approach" by J. L. Hennessy and D. A. Patterson, San Francisco 1995, are taken to ensure that, despite the data copies in the buffer memories, the entire memory of the multicomputer system is accessed uniformly and consistently at any time.
In such multicomputer systems, which a hierarchy of bus systems, it is expedient to have additional intermediate stores (registers) for individual cache lines. These registers may conflict with the cache contents, however. In particular, the case in which data in a write register has to be transferred to the system bus, like data from an intervention register, demands appropriate circuitry for both registers.
Accordingly, an object of the present invention is to reduce the outlay for dealing with such conflicts.